diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-02 19:39:11 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-09 21:07:03 +0100 |
| commit | e0bcb9ca36e4f3081c7e6841283646985ed9676b (patch) | |
| tree | 966a3463050e3ea20ff252e85412b3e176bceb80 /target-sh4/cpu.h | |
| parent | 434254aa5f1a9497710dd10993a72ec434e149a6 (diff) | |
sh7750: handle MMUCR TI bit
When the MMUCR TI bit is set, all the UTLB and ITLB entries should be
flushed.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4/cpu.h')
| -rw-r--r-- | target-sh4/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 366e7986ed..015d59845a 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -167,6 +167,7 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, void do_interrupt(CPUSH4State * env); void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); +void cpu_sh4_invalidate_tlb(CPUSH4State *s); void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, uint32_t mem_value); @@ -222,6 +223,7 @@ enum { /* MMU control register */ #define MMUCR 0x1F000010 #define MMUCR_AT (1<<0) +#define MMUCR_TI (1<<2) #define MMUCR_SV (1<<8) #define MMUCR_URC_BITS (6) #define MMUCR_URC_OFFSET (10) |