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authorAurelien Jarno <aurelien@aurel32.net>2011-01-14 20:39:18 +0100
committerAurelien Jarno <aurelien@aurel32.net>2011-01-14 20:39:18 +0100
commit4f6493ff8a73bbb24ad81b080cc256c1c896b7fb (patch)
tree07bd6488f47f13e7be449b508727e4de05d0b9df /target-sh4/cpu.h
parentfd4bab102c14171f8a5a6b04def6434b75a658a2 (diff)
target-sh4: fix reset on r2d
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4/cpu.h')
-rw-r--r--target-sh4/cpu.h14
1 files changed, 8 insertions, 6 deletions
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index fe33b8afc0..95df6d2a75 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -136,8 +136,6 @@ typedef struct memory_content {
} memory_content;
typedef struct CPUSH4State {
- int id; /* CPU model */
-
uint32_t flags; /* general execution flags */
uint32_t gregs[24]; /* general registers */
float32 fregs[32]; /* floating point registers */
@@ -173,14 +171,18 @@ typedef struct CPUSH4State {
uint32_t expevt; /* exception event register */
uint32_t intevt; /* interrupt event register */
+ tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
+ tlb_t utlb[UTLB_SIZE]; /* unified translation table */
+
+ uint32_t ldst;
+
+ CPU_COMMON
+
+ int id; /* CPU model */
uint32_t pvr; /* Processor Version Register */
uint32_t prr; /* Processor Revision Register */
uint32_t cvr; /* Cache Version Register */
- uint32_t ldst;
-
- CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
- tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
void *intc_handle;
int intr_at_halt; /* SR_BL ignored during sleep */
memory_content *movcal_backup;