aboutsummaryrefslogtreecommitdiff
path: root/target-ppc
diff options
context:
space:
mode:
authorAnton Blanchard <anton@samba.org>2014-03-25 13:40:26 +1100
committerAndreas Färber <afaerber@suse.de>2014-03-27 15:49:16 +0100
commitd6fb330f70831180c69899a4f8ba1a7a5fdce45c (patch)
tree26b50cf9ac2416f34bef6fa87b7f4cfd4ba4e822 /target-ppc
parent6f1834a2baa2f2688efaa7756d000876c7898d13 (diff)
downloadqemu-arm-d6fb330f70831180c69899a4f8ba1a7a5fdce45c.tar.gz
target-ppc: POWER8 supports the MSR_LE bit
Add MSR_LE to the msr_mask for POWER8. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Cédric Le Goater <clg@fr.ibm.com> Tested-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-ppc')
-rw-r--r--target-ppc/translate_init.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 7f53c33eaf..a82c8f9504 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7175,7 +7175,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S;
- pcc->msr_mask = 0x800000000284FF36ULL;
+ pcc->msr_mask = 0x800000000284FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;