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authorBharata B Rao <bharata@linux.vnet.ibm.com>2015-11-06 13:12:59 +0530
committerDavid Gibson <david@gibson.dropbear.id.au>2015-11-11 11:05:30 +1100
commitba3ecda05e933acf6fff618716b6f6d2ed6a5a07 (patch)
tree8fc98ad1a4460346401cd383a9fbf08e153b85d9 /target-ppc
parenta77067f6ac9b17beefea506ce5f514072fe3fcf4 (diff)
downloadqemu-arm-ba3ecda05e933acf6fff618716b6f6d2ed6a5a07.tar.gz
ppc: Add/Re-introduce MMU model definitions needed by PR KVM
Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and 2.07) removed the mmu_model definition POWERPC_MMU_2_06a which is needed by PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting of PR KVM guest. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc')
-rw-r--r--target-ppc/cpu.h6
-rw-r--r--target-ppc/mmu_helper.c8
2 files changed, 14 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index b34aed6a19..31c6fee6f4 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -122,9 +122,15 @@ enum powerpc_mmu_t {
/* Architecture 2.06 variant */
POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
| POWERPC_MMU_AMR | 0x00000003,
+ /* Architecture 2.06 "degraded" (no 1T segments) */
+ POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
+ | 0x00000003,
/* Architecture 2.07 variant */
POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
| POWERPC_MMU_AMR | 0x00000004,
+ /* Architecture 2.07 "degraded" (no 1T segments) */
+ POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
+ | 0x00000004,
#endif /* defined(TARGET_PPC64) */
};
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index e52d0e56c2..30298d8d4a 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1295,7 +1295,9 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
case POWERPC_MMU_64B:
case POWERPC_MMU_2_03:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_07:
+ case POWERPC_MMU_2_07a:
dump_slb(f, cpu_fprintf, env);
break;
#endif
@@ -1435,7 +1437,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
case POWERPC_MMU_64B:
case POWERPC_MMU_2_03:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_07:
+ case POWERPC_MMU_2_07a:
return ppc_hash64_get_phys_page_debug(env, addr);
#endif
@@ -1939,7 +1943,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
case POWERPC_MMU_64B:
case POWERPC_MMU_2_03:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_07:
+ case POWERPC_MMU_2_07a:
#endif /* defined(TARGET_PPC64) */
tlb_flush(CPU(cpu), 1);
break;
@@ -2013,7 +2019,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
case POWERPC_MMU_64B:
case POWERPC_MMU_2_03:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_07:
+ case POWERPC_MMU_2_07a:
/* tlbie invalidate TLBs for all segments */
/* XXX: given the fact that there are too many segments to invalidate,
* and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,