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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2015-08-17 17:34:10 +1000
committerRichard Henderson <rth@twiddle.net>2015-09-11 08:15:28 -0700
commit97ed5ccdee95f0b98bedc601ff979e368583472c (patch)
tree5ee711528010f3700f13983b8222c2ca7ae85c83 /target-ppc
parentba9cef7b6e487a5a8969db81d09b8eec8a2b50c6 (diff)
downloadqemu-arm-97ed5ccdee95f0b98bedc601ff979e368583472c.tar.gz
tlb: Add "ifetch" argument to cpu_mmu_index()
This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-ppc')
-rw-r--r--target-ppc/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 6f76674a4c..406d308960 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1250,7 +1250,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
#define MMU_MODE1_SUFFIX _kernel
#define MMU_MODE2_SUFFIX _hypv
#define MMU_USER_IDX 0
-static inline int cpu_mmu_index (CPUPPCState *env)
+static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
{
return env->mmu_idx;
}