path: root/target-ppc
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authorTom Musta <tommusta@gmail.com>2014-03-31 16:03:57 -0500
committerAlexander Graf <agraf@suse.de>2014-04-08 11:20:01 +0200
commit80189035de73f30e42a7f933c45cccfc4b0c56e9 (patch)
treef6aa76e916362c32fe0c60c3aad24041995f4f17 /target-ppc
parent0453099b7d20c9fc2946ed74f1d965ae4d173d19 (diff)
target-ppc: Define Endian-Correct Accessors for VSR Field Access
This change defines accessors for VSR doubleword and word fields that are correct from a host Endian perspective. This allows code to use the Power ISA indexing numbers in code. For example, the xscvdpsxws instruction has a target VSR that looks like this: 0 32 64 127 +-----------+--------+-----------+-----------+ | undefined | SW | undefined | undefined | +-----------+--------+-----------+-----------+ VSX helper code will use VsrW(1) to access this field. Signed-off-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
1 files changed, 8 insertions, 0 deletions
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 691d5724ed..d79aae9dbe 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1782,6 +1782,14 @@ typedef union _ppc_vsr_t {
float64 f64[2];
} ppc_vsr_t;
+#define VsrW(i) u32[i]
+#define VsrD(i) u64[i]
+#define VsrW(i) u32[3-(i)]
+#define VsrD(i) u64[1-(i)]
static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
if (n < 32) {