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authorAnton Blanchard <anton@samba.org>2014-03-25 13:40:29 +1100
committerAndreas Färber <afaerber@suse.de>2014-03-27 16:15:34 +0100
commit76ac9940c3114db35df92582f3549d9a64a369c4 (patch)
tree3395355145d9ea8f7794cbb3a2980d44c02f33b3 /target-ppc
parent5b2b7dc4e5ed10d439d1aac86879299d9f620f5b (diff)
downloadqemu-arm-76ac9940c3114db35df92582f3549d9a64a369c4.tar.gz
target-ppc: MSR_POW not supported on POWER7/7+/8
Remove MSR_POW from the msr_mask for POWER7/7P/8. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Cédric Le Goater <clg@fr.ibm.com> Tested-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-ppc')
-rw-r--r--target-ppc/translate_init.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 87c00a1af3..d07e186416 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7075,7 +7075,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206;
- pcc->msr_mask = 0x800000000284FF37ULL;
+ pcc->msr_mask = 0x800000000280FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -7118,7 +7118,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206;
- pcc->msr_mask = 0x800000000284FF37ULL;
+ pcc->msr_mask = 0x800000000280FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -7175,7 +7175,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S;
- pcc->msr_mask = 0x800000000284FF37ULL;
+ pcc->msr_mask = 0x800000000280FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;