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authorCyril Bur <cyril.bur@au1.ibm.com>2015-03-02 17:55:38 +1100
committerAlexander Graf <agraf@suse.de>2015-03-09 15:00:07 +0100
commit3ba55e399f7637d2b4054bcc30228cd2d0883823 (patch)
tree18242d4eac1fe091f14732da0251f187b9718848 /target-ppc
parent6494ad9bf4f6e1561f078337d6d82018fd6e7516 (diff)
downloadqemu-arm-3ba55e399f7637d2b4054bcc30228cd2d0883823.tar.gz
PPC: Introduce the Virtual Time Base (VTB) SPR register
This patch adds basic support for the VTB. PowerISA: The Virtual Time Base (VTB) is a 64-bit incrementing counter. Virtual Time Base increments at the same rate as the Time Base until its value becomes 0xFFFF_FFFF_FFFF_FFFF (2 64 - 1); at the next increment its value becomes 0x0000_0000_0000_0000. There is no interrupt or other indication when this occurs. The operation of the Virtual Time Base has the following additional properties. 1. Loading a GPR from the Virtual Time Base has no effect on the accuracy of the Virtual Time Base. 2. Copying the contents of a GPR to the Virtual Time Base replaces the contents of the Virtual Time Base with the contents of the GPR. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
-rw-r--r--target-ppc/cpu.h1
-rw-r--r--target-ppc/translate_init.c10
2 files changed, 11 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index b706b9fdf6..abc3545846 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1624,6 +1624,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_MD_DBRAM1 (0x32A)
#define SPR_RCPU_L2U_RA3 (0x32B)
#define SPR_TAR (0x32F)
+#define SPR_VTB (0x351)
#define SPR_440_INV0 (0x370)
#define SPR_440_INV1 (0x371)
#define SPR_440_INV2 (0x372)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index df1a62c4c6..d74f4f024d 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7819,6 +7819,15 @@ static void gen_spr_power8_ebb(CPUPPCState *env)
KVM_REG_PPC_BESCR, 0x00000000);
}
+/* Virtual Time Base */
+static void gen_spr_vtb(CPUPPCState *env)
+{
+ spr_register(env, SPR_VTB, "VTB",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_tbl, SPR_NOACCESS,
+ 0x00000000);
+}
+
static void gen_spr_power8_fscr(CPUPPCState *env)
{
#if defined(CONFIG_USER_ONLY)
@@ -7881,6 +7890,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
gen_spr_power8_pmu_sup(env);
gen_spr_power8_pmu_user(env);
gen_spr_power8_tm(env);
+ gen_spr_vtb(env);
}
if (version < BOOK3S_CPU_POWER8) {
gen_spr_book3s_dbg(env);