diff options
| author | David Gibson <david@gibson.dropbear.id.au> | 2016-01-15 16:12:09 +1100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-01-30 23:49:27 +1100 |
| commit | 61a36c9b5a12889994e6c45f4a175efcd63936db (patch) | |
| tree | fd7f7c170caf817749400c3ba80bb68b7320941e /target-ppc | |
| parent | 4693364f31016cc08d79d1673c3f735a4f95fd89 (diff) | |
target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs
When HPTEs are removed or modified by hypercalls on spapr, we need to
invalidate the relevant pages in the qemu TLB.
Currently we do that by doing some complicated calculations to work out the
right encoding for the tlbie instruction, then passing that to
ppc_tlb_invalidate_one()... which totally ignores the argument and flushes
the whole tlb.
Avoid that by adding a new flush-by-hpte helper in mmu-hash64.c.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/mmu-hash64.c | 12 | ||||
| -rw-r--r-- | target-ppc/mmu-hash64.h | 3 |
2 files changed, 15 insertions, 0 deletions
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index f4c25b7d14..565a0f484a 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -708,3 +708,15 @@ void ppc_hash64_store_hpte(PowerPCCPU *cpu, env->htab_base + pte_index + HASH_PTE_SIZE_64 / 2, pte1); } } + +void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, + target_ulong pte_index, + target_ulong pte0, target_ulong pte1) +{ + /* + * XXX: given the fact that there are too many segments to + * invalidate, and we still don't have a tlb_flush_mask(env, n, + * mask) in QEMU, we just invalidate all TLBs + */ + tlb_flush(CPU(cpu), 1); +} diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index 24fd2c47ef..293a9514db 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -13,6 +13,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw, int mmu_idx); void ppc_hash64_store_hpte(PowerPCCPU *cpu, target_ulong index, target_ulong pte0, target_ulong pte1); +void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, + target_ulong pte_index, + target_ulong pte0, target_ulong pte1); #endif /* |