diff options
| author | Alexander Graf <agraf@suse.de> | 2012-01-19 19:51:50 +0100 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2012-02-02 02:47:45 +0100 |
| commit | 53319166318f365db3bb72cf5a80618211ecf9df (patch) | |
| tree | 8f1ae4200594deb62c71668039983295a17d9932 /target-ppc | |
| parent | 2c9732dbc0df8c7c40c945b6558da8a448b8c069 (diff) | |
PPC: e500: msync is 440 only, e500 has real sync
The e500 CPUs don't use 440's msync which falls on the same opcode IDs,
but instead use the real powerpc sync instruction. This is important,
since the invalid mask differs between the two.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/translate.c | 3 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 6 |
2 files changed, 4 insertions, 5 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 66eae30209..18d52a983a 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -8579,8 +8579,7 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE, PPC2_BOOKE206), -GEN_HANDLER_E(msync, 0x1F, 0x16, 0x12, 0x03FFF801, - PPC_BOOKE, PPC2_BOOKE206), +GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE, PPC2_BOOKE206), GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index f5fcd1e936..b14a98c2b0 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -4371,7 +4371,7 @@ static void init_proc_e300 (CPUPPCState *env) PPC_WRTEE | PPC_RFDI | \ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ - PPC_MEM_TLBSYNC | PPC_TLBIVAX) + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC) #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206) #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL) #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206) @@ -4390,7 +4390,7 @@ static void init_proc_e300 (CPUPPCState *env) PPC_WRTEE | PPC_RFDI | \ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ - PPC_MEM_TLBSYNC | PPC_TLBIVAX) + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC) #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206) #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL) #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206) @@ -4411,7 +4411,7 @@ static void init_proc_e300 (CPUPPCState *env) PPC_FLOAT | PPC_FLOAT_FRES | \ PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \ PPC_FLOAT_STFIWX | PPC_WAIT | \ - PPC_MEM_TLBSYNC | PPC_TLBIVAX) + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC) #define POWERPC_INSNS2_e500mc (PPC2_BOOKE206) #define POWERPC_MSRM_e500mc (0x000000001402FB36ULL) #define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206) |