diff options
| author | Nathan Froyd <froydnj@codesourcery.com> | 2010-02-23 12:21:31 -0800 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-27 16:10:50 +0100 |
| commit | ae01847f9cbbf9b80252cd36ec645ee821809037 (patch) | |
| tree | 722eacb605abb20abb671076684d08606f34efd5 /target-ppc/translate.c | |
| parent | e6bba2ef49670167694b227df13fc8461debbcd5 (diff) | |
target-ppc: fix SPE evsplat* instructions
The shifts in the gen_evsplat* functions were expecting rA to be masked,
not extracted, and so used the wrong shift amounts to sign-extend or pad
with zeroes.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d4e81ce89b..0b11fda880 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7001,7 +7001,7 @@ static inline void gen_evmergelohi(DisasContext *ctx) } static inline void gen_evsplati(DisasContext *ctx) { - uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27; + uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; #if defined(TARGET_PPC64) tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); @@ -7012,7 +7012,7 @@ static inline void gen_evsplati(DisasContext *ctx) } static inline void gen_evsplatfi(DisasContext *ctx) { - uint64_t imm = rA(ctx->opcode) << 11; + uint64_t imm = rA(ctx->opcode) << 27; #if defined(TARGET_PPC64) tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |