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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2016-03-21 13:52:39 +0100
committerDavid Gibson <david@gibson.dropbear.id.au>2016-03-24 11:17:34 +1100
commiteb5ceb4d389b1b34b210baf9fa49b48bacb2538b (patch)
treebb66952a6a3d82b02fc0090e53c95a0528e85b81 /target-ppc/cpu.h
parenta6eabb9e5908ddf521ea372651b8321ffa804bd8 (diff)
downloadqemu-arm-eb5ceb4d389b1b34b210baf9fa49b48bacb2538b.tar.gz
ppc: Add dummy CIABR SPR
We should implement HW breakpoint/watchpoint, qemu supports them... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/cpu.h')
-rw-r--r--target-ppc/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index a3c4fb112a..29c48600d9 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1393,6 +1393,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_PSPB (0x09F)
#define SPR_DAWR (0x0B4)
#define SPR_RPR (0x0BA)
+#define SPR_CIABR (0x0BB)
#define SPR_DAWRX (0x0BC)
#define SPR_HFSCR (0x0BE)
#define SPR_VRSAVE (0x100)