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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2016-06-03 14:11:19 +0200
committerDavid Gibson <david@gibson.dropbear.id.au>2016-06-07 10:17:45 +1000
commit932ccbdd48cea5b86f895bdc7d6b409d24aa81cd (patch)
tree78404bda8cf2ff2b6f5ab1886751791af30676b4 /target-ppc/cpu.h
parent1ea1eefcbbcbea91ab295bd5c8c5330d1f458174 (diff)
downloadqemu-arm-932ccbdd48cea5b86f895bdc7d6b409d24aa81cd.tar.gz
ppc: Better figure out if processor has HV mode
We use an env. flag which is set to the initial value of MSR_HVB in the msr_mask. We also adjust the POWER8 mask to set SHV. Also use this to adjust ctx.hv so that it is *set* when the processor doesn't have an HV mode (970 with Apple mode for example), thus enabling hypervisor instructions/SPRs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: ctx.hv used to be defined only for the hypervisor kernel (HV=1|PR=0). It is now defined also when PR=1 and conditions are fixed accordingly. stripped unwanted tabs.] Signed-off-by: C├ędric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/cpu.h')
-rw-r--r--target-ppc/cpu.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 98a24a50f3..d8f8f7e233 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1050,6 +1050,10 @@ struct CPUPPCState {
hwaddr mpic_iack;
/* true when the external proxy facility mode is enabled */
bool mpic_proxy;
+ /* set when the processor has an HV mode, thus HV priv
+ * instructions and SPRs are diallowed if MSR:HV is 0
+ */
+ bool has_hv_mode;
#endif
/* Those resources are used only during code translation */