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| author | Alexander Graf <agraf@suse.de> | 2014-01-19 17:49:11 +0100 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:35 +0200 |
| commit | ea71258da4b8141d8a808d94518a0964c0f92810 (patch) | |
| tree | 253b6f10663b08f0846bd40a08821501a15495dd /target-ppc/cpu.h | |
| parent | d2ea2bf740c515de41f45e4d6f36683db3458881 (diff) | |
PPC: Properly emulate L1CSR0 and L1CSR1
There are 2 L1 cache control registers - one for data (L1CSR0) and
one for instructions (L1CSR1).
Emulate both of them well enough to give the guest the illusion that
it could actually do anything about its caches.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index f36c90b47b..b035e91316 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1716,6 +1716,18 @@ static inline int cpu_mmu_index (CPUPPCState *env) /* External Input Interrupt Directed to Guest State */ #define EPCR_EXTGS (1 << 31) +#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ +#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */ +#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */ +#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ +#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ + +#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ +#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */ +#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */ +#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ +#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ + /*****************************************************************************/ /* PowerPC Instructions types definitions */ enum { |