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authorGreg Kurz <gkurz@linux.vnet.ibm.com>2014-05-19 19:59:05 +0200
committerAlexander Graf <agraf@suse.de>2014-06-16 13:24:36 +0200
commit382d2db62bcb34dff7febc270783d5ff662ced7a (patch)
tree6997e3caabed16552509587067e8daa7713c8f11 /target-ppc/cpu-qom.h
parent0c967de9c00321f893a57617a4e3dfcda05266f5 (diff)
downloadqemu-arm-382d2db62bcb34dff7febc270783d5ff662ced7a.tar.gz
target-ppc: Introduce callback for interrupt endianness
POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR special purpose register to decide the endianness to use when entering interrupt handlers. When running a Linux guest, this provides a hint on the endianness used by the kernel. And when it comes to dumping a guest, the information is needed to write ELF headers using the kernel endianness. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> [agraf: change subject line] Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu-qom.h')
-rw-r--r--target-ppc/cpu-qom.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index d926d9369e..046ea0effa 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -76,6 +76,7 @@ typedef struct PowerPCCPUClass {
int (*handle_mmu_fault)(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
int mmu_idx);
#endif
+ bool (*interrupts_big_endian)(PowerPCCPU *cpu);
} PowerPCCPUClass;
/**