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authorDavid Gibson <david@gibson.dropbear.id.au>2013-04-07 19:08:19 +0000
committerAlexander Graf <agraf@suse.de>2013-04-26 23:02:41 +0200
commit0cbad81f70546b58f08de3225f1eca7a8b869b09 (patch)
tree9a0adc74e12dbbe58e60ad1f1ebcb7ce986a589c /target-ppc/cpu-qom.h
parentf36951c19f15f3c053a31234bd2c297d86c1a052 (diff)
downloadqemu-arm-0cbad81f70546b58f08de3225f1eca7a8b869b09.tar.gz
pseries: Fixes and enhancements to L1 cache properties
PAPR requires that the device tree's CPU nodes have several properties with information about the L1 cache. We already create two of these properties, but with incorrect names - "[id]cache-block-size" instead of "[id]-cache-block-size" (note the extra hyphen). We were also missing some of the required cache properties. This patch adds the [id]-cache-line-size properties (which have the same values as the block size properties in all current cases). We also add the [id]-cache-size properties. Adding the cache sizes requires some extra infrastructure in the general target-ppc code to (optionally) set the cache sizes for various CPUs. The CPU family descriptions in translate_init.c can set these sizes - this patch adds correct information for POWER7, I'm leaving other CPU types to people who have a physical example to verify against. In addition, for -cpu host we take the values advertised by the host (if available) and use those to override the information based on PVR. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu-qom.h')
-rw-r--r--target-ppc/cpu-qom.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index c27cef7e32..eb03a00799 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -63,6 +63,7 @@ typedef struct PowerPCCPUClass {
powerpc_input_t bus_model;
uint32_t flags;
int bfd_mach;
+ uint32_t l1_dcache_size, l1_icache_size;
#if defined(TARGET_PPC64)
const struct ppc_segment_page_sizes *sps;
#endif