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authorAndreas Färber <afaerber@suse.de>2013-09-04 02:19:44 +0200
committerAndreas Färber <afaerber@suse.de>2014-03-13 19:52:47 +0100
commit00c8cb0a36f51a6866a83c08962d12a0eb21864b (patch)
tree3fc05321f0f72aa3d7612efcce6b53ede066d909 /target-openrisc
parent31b030d4abc5bea89c2b33b39d3b302836f6b6ee (diff)
cputlb: Change tlb_flush() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-openrisc')
-rw-r--r--target-openrisc/cpu.c2
-rw-r--r--target-openrisc/interrupt.c2
-rw-r--r--target-openrisc/interrupt_helper.c2
-rw-r--r--target-openrisc/sys_helper.c2
4 files changed, 4 insertions, 4 deletions
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index a00369bef5..08e724c126 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -47,7 +47,7 @@ static void openrisc_cpu_reset(CPUState *s)
memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq));
#endif
- tlb_flush(&cpu->env, 1);
+ tlb_flush(s, 1);
/*tb_flush(&cpu->env); FIXME: Do we need it? */
cpu->env.pc = 0x100;
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index e312300853..3de567eee8 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -43,7 +43,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
/* For machine-state changed between user-mode and supervisor mode,
we need flush TLB when we enter&exit EXCP. */
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
env->esr = env->sr;
env->sr &= ~SR_DME;
diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c
index 844648f780..819405701d 100644
--- a/target-openrisc/interrupt_helper.c
+++ b/target-openrisc/interrupt_helper.c
@@ -51,7 +51,7 @@ void HELPER(rfe)(CPUOpenRISCState *env)
}
if (need_flush_tlb) {
- tlb_flush(&cpu->env, 1);
+ tlb_flush(cs, 1);
}
#endif
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index f1ff3adca9..fedcbed4f7 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(0, 17): /* SR */
if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
(rb & (SR_IME | SR_DME | SR_SM))) {
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
}
env->sr = rb;
env->sr |= SR_FO; /* FO is const equal to 1 */