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authorRichard Henderson <rth@twiddle.net>2015-10-13 22:07:49 +0000
committerRichard Henderson <rth@twiddle.net>2015-10-28 10:57:16 -0700
commit522a0d4e3c0d397ffb45ec400d8cbd426dad9d17 (patch)
tree47bf23d369e201fe8e982097a5fdd5437f88bdfa /target-openrisc/translate.c
parent496fedddce9a575111df4f912fb9e361037531ed (diff)
target-*: Advance pc after recognizing a breakpoint
Some targets already had this within their logic, but make sure it's present for all targets. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-openrisc/translate.c')
-rw-r--r--target-openrisc/translate.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index b66fde18fe..606490a47b 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1665,6 +1665,11 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
tcg_gen_movi_tl(cpu_pc, dc->pc);
gen_exception(dc, EXCP_DEBUG);
dc->is_jmp = DISAS_UPDATE;
+ /* The address covered by the breakpoint must be included in
+ [tb->pc, tb->pc + tb->size) in order to for it to be
+ properly cleared -- thus we increment the PC here so that
+ the logic setting tb->size below does the right thing. */
+ dc->pc += 4;
break;
}