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authorAndré Draszik <git@andred.net>2016-07-26 00:42:45 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2016-09-23 07:07:29 +0100
commite9deaad8a58c899dc32e9fdeff9e533070e79dca (patch)
treef77ead1aeb7382a6179f9f323ffba1fd6fde5236 /target-mips
parent430da7a81d356e368ccd88dcca60f38da9aa5b9a (diff)
downloadqemu-arm-e9deaad8a58c899dc32e9fdeff9e533070e79dca.tar.gz
target-mips: add 24KEc CPU definition
Define a new CPU definition supporting 24KEc cores, similar to the existing 24Kc, but with added support for DSP instructions and MIPS16e (and without FPU). Signed-off-by: André Draszik <git@andred.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate_init.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 39ed5c4c1b..6ae23e476f 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -256,6 +256,28 @@ static const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000,
},
{
+ .name = "24KEc",
+ .CP0_PRid = 0x00019600,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ /* we have a DSP, but no FPU */
+ .CP0_Status_rw_bitmask = 0x1378FF1F,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
.name = "24Kf",
.CP0_PRid = 0x00019300,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |