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authorLeon Alrae <leon.alrae@imgtec.com>2016-03-15 09:59:36 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2016-03-30 09:13:59 +0100
commita9a95061715ca09abff56a3f239f704c410912c2 (patch)
treef07a6150f00f905bb3a86c3b8dc50d2cd97d7d49 /target-mips
parentbff384a4fbd5d0e86939092e74e766ef0f5f592c (diff)
downloadqemu-arm-a9a95061715ca09abff56a3f239f704c410912c2.tar.gz
target-mips: enable CM GCR in MIPS64R6-generic CPU
Indicate that in the MIPS64R6-generic CPU the memory-mapped Global Configuration Register Space is implemented. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate_init.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 3192db0960..b44df9e5da 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -663,7 +663,8 @@ static const mips_def_t mips_defs[] =
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
+ (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
(1 << CP0C3_RXI) | (1 << CP0C3_LPA),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |