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authorAleksandar Markovic <aleksandar.markovic@imgtec.com>2016-06-10 11:57:37 +0200
committerLeon Alrae <leon.alrae@imgtec.com>2016-06-24 13:43:53 +0100
commit77be419980114d75605811e1681115d0919cfa1a (patch)
tree5ee60eba85594e3f5c8d987bfc145e0e76130ff6 /target-mips
parent599bc5e89c46f95f86ccad0d747d041c89a28806 (diff)
downloadqemu-arm-77be419980114d75605811e1681115d0919cfa1a.tar.gz
target-mips: Add FCR31's FS bit definition
Add preprocessor definition of FCR31's FS bit, and update related code for setting this bit. Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/cpu.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index bc0c905041..c2da5ecf7c 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -113,6 +113,7 @@ struct CPUMIPSFPUContext {
/* fcsr */
uint32_t fcr31_rw_bitmask;
uint32_t fcr31;
+#define FCR31_FS 24
#define FCR31_ABS2008 19
#define FCR31_NAN2008 18
#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
@@ -850,7 +851,7 @@ static inline void restore_rounding_mode(CPUMIPSState *env)
static inline void restore_flush_mode(CPUMIPSState *env)
{
- set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
+ set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
&env->active_fpu.fp_status);
}