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authorLeon Alrae <leon.alrae@imgtec.com>2016-03-25 13:49:35 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2016-03-30 09:14:00 +0100
commit40d48212f934d4deab40ffe84a0f9c4c553d4742 (patch)
tree984fdc7552351a4984f7bc171806eafbc9de78c0 /target-mips
parent25a611e3e4a560c034c942527c643dfc990c7491 (diff)
downloadqemu-arm-40d48212f934d4deab40ffe84a0f9c4c553d4742.tar.gz
target-mips: check CP0 enabled for CACHE instruction also in R6
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a5b8805f77..65f2caff3e 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17194,6 +17194,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
/* Treat as NOP. */
break;
case R6_OPC_CACHE:
+ check_cp0_enabled(ctx);
/* Treat as NOP. */
break;
case R6_OPC_SC: