diff options
| author | Nathan Froyd <froydnj@codesourcery.com> | 2009-08-25 08:20:00 -0700 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-08-25 18:05:27 +0200 |
| commit | fa31af0e63c5629d0bdc63eb87c1e44abd4fdb9e (patch) | |
| tree | 324fc5ca7a833a786d9202e9d29178246648680c /target-mips | |
| parent | 4e6f6d4c20252c6900f01787559b97a559c0b402 (diff) | |
target-mips: fix conditional moves off fp condition codes
Conditional moves off fp condition codes were using the result of
get_fp_bit to isolate and test the relevant condition code. However,
get_fp_bit returns the bit number of the condition code, not a
bitmask. (Compare the use of get_fp_bit in gen_compute_branch1, for
instance.)
Fixed by shifting a bitmask into place using the result of get_fp_bit in
the relevant functions (gen_mov{ci,cf_s,cf_d,cf_ps}).
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 6a1273f036..a2b2edbbd2 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -5896,7 +5896,7 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) l1 = gen_new_label(); t0 = tcg_temp_new_i32(); - tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); tcg_temp_free_i32(t0); if (rs == 0) { @@ -5918,7 +5918,7 @@ static inline void gen_movcf_s (int fs, int fd, int cc, int tf) else cond = TCG_COND_NE; - tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); gen_load_fpr32(t0, fs); gen_store_fpr32(t0, fd); @@ -5938,7 +5938,7 @@ static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int t else cond = TCG_COND_NE; - tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); tcg_temp_free_i32(t0); fp0 = tcg_temp_new_i64(); @@ -5960,13 +5960,13 @@ static inline void gen_movcf_ps (int fs, int fd, int cc, int tf) else cond = TCG_COND_NE; - tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); gen_load_fpr32(t0, fs); gen_store_fpr32(t0, fd); gen_set_label(l1); - tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc+1)); tcg_gen_brcondi_i32(cond, t0, 0, l2); gen_load_fpr32h(t0, fs); gen_store_fpr32h(t0, fd); |