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authorPetar Jovanovic <petar.jovanovic@imgtec.com>2013-07-01 01:54:47 +0200
committerAurelien Jarno <aurelien@aurel32.net>2013-07-29 00:27:36 +0200
commitd36c231f4b7386bd8230aa17d362b925aa419b2f (patch)
tree49513570a018c658582d8fb24b88bb8487988489 /target-mips
parent05b3274b6bedb68ff78b76c642e17e97f3181c2f (diff)
target-mips: fix mipsdsp_trunc16_sat16_round
This change corrects rounding and saturation of Q31 fractional value in mipsdsp_trunc16_sat16_round(). Overflow detection was incorrect for the corner case for PRECRQ_RS.PH, and this test case is also part of the change. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/dsp_helper.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index c718a786e1..93f5d9e023 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -648,16 +648,22 @@ static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t a, uint16_t b,
static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a,
CPUMIPSState *env)
{
- int64_t temp;
+ uint16_t temp;
- temp = (int32_t)a + 0x00008000;
- if (a > (int)0x7fff8000) {
- temp = 0x7FFFFFFF;
+ /*
+ * The value 0x00008000 will be added to the input Q31 value, and the code
+ * needs to check if the addition causes an overflow. Since a positive value
+ * is added, overflow can happen in one direction only.
+ */
+ if (a > 0x7FFF7FFF) {
+ temp = 0x7FFF;
set_DSPControl_overflow_flag(1, 22, env);
+ } else {
+ temp = ((a + 0x8000) >> 16) & 0xFFFF;
}
- return (temp >> 16) & 0xFFFF;
+ return temp;
}
static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a,