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authorLeon Alrae <leon.alrae@imgtec.com>2014-11-06 10:29:38 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2014-11-07 14:15:28 +0000
commit854795753c6efceda1d172851e2bae4b47a492be (patch)
tree0a1006760fee14fcd9e0e9c11b725b918047ed32 /target-mips
parente30614d51780f27c53b196da793c3fb89f1f620f (diff)
target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ
New R6 COP1 conditional branches currently don't have delay slot. Fixing this by setting MIPS_HFLAG_BDS32 flag which is required for branches having 4-byte delay slot. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index d6722e1a18..194d4fb42a 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -8104,6 +8104,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
ctx->hflags, btarget);
ctx->btarget = btarget;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
out:
tcg_temp_free_i64(t0);