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authorLeon Alrae <leon.alrae@imgtec.com>2015-09-09 14:45:36 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2015-09-18 09:20:48 +0100
commitdb77d8523909b32d798cd2c80de422b68f9e5c42 (patch)
treef933fcb6ca3fd8afd845c08439bab1c73f4d2553 /target-mips/translate.c
parent3adafef2f35d9061b56a09071b2589b9e0b36f76 (diff)
downloadqemu-arm-db77d8523909b32d798cd2c80de422b68f9e5c42.tar.gz
target-mips: add missing restriction in DAUI instruction
rs cannot be the zero register, Reserved Instruction exception must be signalled for this case. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/translate.c')
-rw-r--r--target-mips/translate.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index cd0cf8b655..0883782b8c 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19525,7 +19525,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
/* OPC_DAUI */
check_mips_64(ctx);
- if (rt != 0) {
+ if (rs == 0) {
+ generate_exception(ctx, EXCP_RI);
+ } else if (rt != 0) {
TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rs);
tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);