aboutsummaryrefslogtreecommitdiff
path: root/target-mips/translate.c
diff options
context:
space:
mode:
authorLeon Alrae <leon.alrae@imgtec.com>2015-09-09 12:44:25 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2015-09-18 09:20:48 +0100
commitd54a299b83a07642c85a22bfe19b69ca4def9ec4 (patch)
treee81c778717e27d4ee9525482136669666f7daa70 /target-mips/translate.c
parentdb77d8523909b32d798cd2c80de422b68f9e5c42 (diff)
downloadqemu-arm-d54a299b83a07642c85a22bfe19b69ca4def9ec4.tar.gz
target-mips: correct MTC0 instruction on MIPS64
MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0 register. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/translate.c')
-rw-r--r--target-mips/translate.c18
1 files changed, 7 insertions, 11 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 0883782b8c..a59b6704a1 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4765,12 +4765,6 @@ static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
tcg_temp_free_i32(t0);
}
-static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
-{
- tcg_gen_ext32s_tl(arg, arg);
- tcg_gen_st_tl(arg, cpu_env, off);
-}
-
static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
@@ -5629,12 +5623,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 5:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
+ tcg_gen_st_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
+ tcg_gen_st_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
@@ -5884,7 +5880,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 14:
switch (sel) {
case 0:
- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_EPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
rn = "EPC";
break;
default:
@@ -6057,7 +6053,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case 0:
/* EJTAG support */
- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_DEPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
rn = "DEPC";
break;
default:
@@ -6160,7 +6156,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 30:
switch (sel) {
case 0:
- gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_ErrorEPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default: