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authorPetar Jovanovic <petar.jovanovic@imgtec.com>2015-08-26 14:12:20 +0200
committerLeon Alrae <leon.alrae@imgtec.com>2015-09-18 09:20:48 +0100
commitca6c7803d2beae43299a80f4549d36579881fc0b (patch)
treef09c862b46a9e0b380b0d4ac66519fb3b96367df /target-mips/translate.c
parent71f303cd246ae22ce6fdacb3801b5abbca25c409 (diff)
downloadqemu-arm-ca6c7803d2beae43299a80f4549d36579881fc0b.tar.gz
target-mips: remove wrong checks for recip.fmt and rsqrt.fmt
Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither they require any particular mode for its FPU. This patch removes the checks that may break a program that uses these instructions. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/translate.c')
-rw-r--r--target-mips/translate.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 2f1e724139..fadef9e89d 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -9290,7 +9290,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "movn.s";
break;
case OPC_RECIP_S:
- check_cop1x(ctx);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
@@ -9302,7 +9301,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "recip.s";
break;
case OPC_RSQRT_S:
- check_cop1x(ctx);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
@@ -9835,7 +9833,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "movn.d";
break;
case OPC_RECIP_D:
- check_cp1_64bitmode(ctx);
+ check_cp1_registers(ctx, fs | fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
@@ -9847,7 +9845,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "recip.d";
break;
case OPC_RSQRT_D:
- check_cp1_64bitmode(ctx);
+ check_cp1_registers(ctx, fs | fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64();