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authorPaul Burton <paul.burton@imgtec.com>2016-06-27 16:19:11 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2016-07-12 09:10:20 +0100
commita0c8060841f2d56fb3504292c18522b957972e4c (patch)
tree64a3b96903cd8de04b0ce3f3683d05e1a68d8e64 /target-mips/translate.c
parent2d72e7b047d800c9f99262466f65a98684ecca14 (diff)
downloadqemu-arm-a0c8060841f2d56fb3504292c18522b957972e4c.tar.gz
target-mips: support CP0.Config4.AE bit
The read-only Config4.AE bit set denotes extended 10 bits ASID. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/translate.c')
-rw-r--r--target-mips/translate.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 01510b38b1..bab52cb254 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20302,7 +20302,8 @@ void cpu_state_reset(CPUMIPSState *env)
if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
}
- env->CP0_EntryHi_ASID_mask = 0xff;
+ env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ?
+ 0x3ff : 0xff;
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
/* vectored interrupts not implemented, timer on int 7,
no performance counters. */