diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2009-11-22 13:22:54 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-11-22 14:12:19 +0100 |
| commit | 2a6e32dd46967124f12c29eece7aa7fc3f0ee063 (patch) | |
| tree | fa0760fd31f33d71b3a52c3c90d056ce31adc5c6 /target-mips/translate.c | |
| parent | 5499b6ffac490a3a44dcb97e9cebb99f0151d696 (diff) | |
target-mips: make CP0_LLAddr register CPU dependent
Depending on the CPU, CP0_LLAddr is either read-only or read-write,
and the returned value can be shifted by a variable amount of bits.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 63737e2379..e9d92249ef 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -3841,7 +3841,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s case 17: switch (sel) { case 0: - /* ignored */ + gen_helper_mtc0_lladdr(arg); rn = "LLAddr"; break; default: @@ -4998,7 +4998,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int case 17: switch (sel) { case 0: - /* ignored */ + gen_helper_mtc0_lladdr(arg); rn = "LLAddr"; break; default: @@ -8633,6 +8633,9 @@ void cpu_reset (CPUMIPSState *env) env->CP0_Config3 = env->cpu_model->CP0_Config3; env->CP0_Config6 = env->cpu_model->CP0_Config6; env->CP0_Config7 = env->cpu_model->CP0_Config7; + env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask + << env->cpu_model->CP0_LLAddr_shift; + env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; env->SYNCI_Step = env->cpu_model->SYNCI_Step; env->CCRes = env->cpu_model->CCRes; env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; |