path: root/target-mips/op_helper.c
diff options
authorLeon Alrae <leon.alrae@imgtec.com>2015-11-19 19:15:35 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2015-11-24 11:01:03 +0000
commitf93c3a8d0c0c1038dbe1e957eb8ab92671137975 (patch)
tree00969bbc0675fd9851c1678f8c829846221e192c /target-mips/op_helper.c
parent7871abb94c2f4adc39f2487f6edf5e69ba872a65 (diff)
target-mips: flush QEMU TLB when disabling 64-bit addressing
CP0.Status.KX/SX/UX bits are responsible for enabling access to 64-bit Kernel/Supervisor/User Segments. If bit is cleared an access to corresponding segment should generate Address Error Exception. However, the guest may still be able to access some pages belonging to the disabled 64-bit segment because we forget to flush QEMU TLB. This patch fixes it. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/op_helper.c')
1 files changed, 0 insertions, 13 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 056d53b9ef..d2c98c9688 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -23,10 +23,6 @@
#include "exec/cpu_ldst.h"
#include "sysemu/kvm.h"
-static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
/* Exceptions processing helpers */
@@ -1846,15 +1842,6 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
/* TLB management */
-static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
- MIPSCPU *cpu = mips_env_get_cpu(env);
- /* Flush qemu's TLB and discard all shadowed entries. */
- tlb_flush(CPU(cpu), flush_global);
- env->tlb->tlb_in_use = env->tlb->nb_tlb;
static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
/* Discard entries from env->tlb[first] onwards. */