aboutsummaryrefslogtreecommitdiff
path: root/target-mips/op_helper.c
diff options
context:
space:
mode:
authorYongbok Kim <yongbok.kim@imgtec.com>2015-10-29 15:18:39 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2015-10-30 14:35:52 +0000
commitb00c72180c36510bf9b124e190bd520e3b7e1358 (patch)
treef5a64bd037c0b5577e406da3a7d17f1fc1f5080d /target-mips/op_helper.c
parentca2f6bbbce32b7e1ba4fdaf54165ab0dee47a3a5 (diff)
downloadqemu-arm-b00c72180c36510bf9b124e190bd520e3b7e1358.tar.gz
target-mips: add PC, XNP reg numbers to RDHWR
Add Performance Counter (4) and XNP (5) register numbers to RDHWR. Add check_hwrena() to simplify access control checkings. Add RDHWR support to microMIPS R6. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/op_helper.c')
-rw-r--r--target-mips/op_helper.c64
1 files changed, 35 insertions, 29 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 6739fff216..056d53b9ef 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1357,6 +1357,13 @@ void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
{
uint32_t mask = 0x0000000F;
+ if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
+ (env->insn_flags & ISA_MIPS32R6)) {
+ mask |= (1 << 4);
+ }
+ if (env->insn_flags & ISA_MIPS32R6) {
+ mask |= (1 << 5);
+ }
if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
mask |= (1 << 29);
@@ -2185,53 +2192,52 @@ void helper_deret(CPUMIPSState *env)
}
#endif /* !CONFIG_USER_ONLY */
-target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
+static inline void check_hwrena(CPUMIPSState *env, int reg)
{
- if ((env->hflags & MIPS_HFLAG_CP0) ||
- (env->CP0_HWREna & (1 << 0)))
- return env->CP0_EBase & 0x3ff;
- else
- do_raise_exception(env, EXCP_RI, GETPC());
+ if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
+ return;
+ }
+ do_raise_exception(env, EXCP_RI, GETPC());
+}
- return 0;
+target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
+{
+ check_hwrena(env, 0);
+ return env->CP0_EBase & 0x3ff;
}
target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
{
- if ((env->hflags & MIPS_HFLAG_CP0) ||
- (env->CP0_HWREna & (1 << 1)))
- return env->SYNCI_Step;
- else
- do_raise_exception(env, EXCP_RI, GETPC());
-
- return 0;
+ check_hwrena(env, 1);
+ return env->SYNCI_Step;
}
target_ulong helper_rdhwr_cc(CPUMIPSState *env)
{
- if ((env->hflags & MIPS_HFLAG_CP0) ||
- (env->CP0_HWREna & (1 << 2))) {
+ check_hwrena(env, 2);
#ifdef CONFIG_USER_ONLY
- return env->CP0_Count;
+ return env->CP0_Count;
#else
- return (int32_t)cpu_mips_get_count(env);
+ return (int32_t)cpu_mips_get_count(env);
#endif
- } else {
- do_raise_exception(env, EXCP_RI, GETPC());
- }
-
- return 0;
}
target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
{
- if ((env->hflags & MIPS_HFLAG_CP0) ||
- (env->CP0_HWREna & (1 << 3)))
- return env->CCRes;
- else
- do_raise_exception(env, EXCP_RI, GETPC());
+ check_hwrena(env, 3);
+ return env->CCRes;
+}
- return 0;
+target_ulong helper_rdhwr_performance(CPUMIPSState *env)
+{
+ check_hwrena(env, 4);
+ return env->CP0_Performance0;
+}
+
+target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
+{
+ check_hwrena(env, 5);
+ return (env->CP0_Config5 >> CP0C5_XNP) & 1;
}
void helper_pmon(CPUMIPSState *env, int function)