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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2015-08-17 17:34:10 +1000
committerRichard Henderson <rth@twiddle.net>2015-09-11 08:15:28 -0700
commit97ed5ccdee95f0b98bedc601ff979e368583472c (patch)
tree5ee711528010f3700f13983b8222c2ca7ae85c83 /target-mips/op_helper.c
parentba9cef7b6e487a5a8969db81d09b8eec8a2b50c6 (diff)
downloadqemu-arm-97ed5ccdee95f0b98bedc601ff979e368583472c.tar.gz
tlb: Add "ifetch" argument to cpu_mmu_index()
This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-mips/op_helper.c')
-rw-r--r--target-mips/op_helper.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 809a061e29..1aa9e3c9e4 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -3629,7 +3629,7 @@ FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
#if !defined(CONFIG_USER_ONLY)
#define MEMOP_IDX(DF) \
TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
- cpu_mmu_index(env));
+ cpu_mmu_index(env, false));
#else
#define MEMOP_IDX(DF)
#endif
@@ -3685,7 +3685,7 @@ void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
target_ulong addr) \
{ \
wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
- int mmu_idx = cpu_mmu_index(env); \
+ int mmu_idx = cpu_mmu_index(env, false); \
int i; \
MEMOP_IDX(DF) \
ensure_writable_pages(env, addr, mmu_idx, GETRA()); \