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authorAleksandar Markovic <aleksandar.markovic@imgtec.com>2016-06-10 11:57:36 +0200
committerLeon Alrae <leon.alrae@imgtec.com>2016-06-24 13:43:52 +0100
commit599bc5e89c46f95f86ccad0d747d041c89a28806 (patch)
treeac0fde39e6c036c145a5beba89e3a8b9975e0e50 /target-mips/op_helper.c
parent87552089b62fa229d2ff86906e4e779177fb5835 (diff)
downloadqemu-arm-599bc5e89c46f95f86ccad0d747d041c89a28806.tar.gz
target-mips: Implement FCR31's R/W bitmask and related functionalities
This patch implements read and write access rules for Mips floating point control and status register (FCR31). The change can be divided into following parts: - Add fields that will keep FCR31's R/W bitmask in procesor definitions and processor float_status structure. - Add appropriate value for FCR31's R/W bitmask for each supported processor. - Add function for setting snan_bit_is_one, and integrate it in appropriate places. - Modify handling of CTC1 (case 31) instruction to use FCR31's R/W bitmask. - Modify handling user mode executables for Mips, in relation to the bit EF_MIPS_NAN2008 from ELF header, that is in turn related to reading and writing to FCR31. - Modify gdb behavior in relation to FCR31. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/op_helper.c')
-rw-r--r--target-mips/op_helper.c14
1 files changed, 3 insertions, 11 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 7f6e8217b2..69daade24e 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2575,21 +2575,13 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
((arg1 & 0x4) << 22);
break;
case 31:
- if (env->insn_flags & ISA_MIPS32R6) {
- uint32_t mask = 0xfefc0000;
- env->active_fpu.fcr31 = (arg1 & ~mask) |
- (env->active_fpu.fcr31 & mask);
- } else if (!(arg1 & 0x007c0000)) {
- env->active_fpu.fcr31 = arg1;
- }
+ env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
+ (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
break;
default:
return;
}
- /* set rounding mode */
- restore_rounding_mode(env);
- /* set flush-to-zero mode */
- restore_flush_mode(env);
+ restore_fp_status(env);
set_float_exception_flags(0, &env->active_fpu.fp_status);
if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
do_raise_exception(env, EXCP_FPE, GETPC());