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authorLeon Alrae <leon.alrae@imgtec.com>2015-06-09 17:14:13 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2015-06-12 09:05:00 +0100
commit284b731a6ae47b9ebabb9613e753c4d83cf75dd3 (patch)
tree24043a79d29416582fa2489c32419e111715474b /target-mips/op_helper.c
parentb435f3f3d174721382b55bbd0c785ec50c1796a9 (diff)
downloadqemu-arm-284b731a6ae47b9ebabb9613e753c4d83cf75dd3.tar.gz
target-mips: extend selected CP0 registers to 64-bits in MIPS32
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32. Introduce gen_move_low32() function which moves low 32 bits from 64-bit temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on MIPS32. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/op_helper.c')
-rw-r--r--target-mips/op_helper.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index b412f94f82..4dc4970d80 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1997,12 +1997,12 @@ void r4k_helper_tlbr(CPUMIPSState *env)
env->CP0_EntryHi = tlb->VPN | tlb->ASID;
env->CP0_PageMask = tlb->PageMask;
env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
- ((target_ulong)tlb->RI0 << CP0EnLo_RI) |
- ((target_ulong)tlb->XI0 << CP0EnLo_XI) |
+ ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
+ ((uint64_t)tlb->XI0 << CP0EnLo_XI) |
(tlb->C0 << 3) | (tlb->PFN[0] >> 6);
env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
- ((target_ulong)tlb->RI1 << CP0EnLo_RI) |
- ((target_ulong)tlb->XI1 << CP0EnLo_XI) |
+ ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
+ ((uint64_t)tlb->XI1 << CP0EnLo_XI) |
(tlb->C1 << 3) | (tlb->PFN[1] >> 6);
}
}