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authorMaciej W. Rozycki <macro@codesourcery.com>2014-11-20 11:15:34 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2014-12-16 12:45:20 +0000
commit1d725ae952a14b30c84b7bc81b218b8ba77dd311 (patch)
tree2b41de5acdbf012a5b877817e6a0bf0c5573fd27 /target-mips/op_helper.c
parentcbb26c9a122c3f71fb53989817d406a2f6d08662 (diff)
downloadqemu-arm-1d725ae952a14b30c84b7bc81b218b8ba77dd311.tar.gz
target-mips: Also apply the CP0.Status mask to MTTC0
Make CP0.Status writes made with the MTTC0 instruction respect this register's mask just like all the other places. Also preserve the current values of masked out bits. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/op_helper.c')
-rw-r--r--target-mips/op_helper.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 1267ef297c..7e632f6875 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1413,9 +1413,10 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
+ uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- other->CP0_Status = arg1 & ~0xf1000018;
+ other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
sync_c0_status(env, other, other_tc);
}