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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-11 02:24:14 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-11 02:24:14 +0000
commitb48cfdffd9f15432355c8e4ed9d2781eab9e4358 (patch)
tree1f2fd6d73b632641afb3bbeb344247aa0647ae9c /target-mips/mips-defs.h
parent2423f6601a19fa0ac4eac360de9d3fe80a18d715 (diff)
Throw RI for invalid MFMC0-class instructions. Introduce optional
MIPS_STRICT_STANDARD define to adhere more to the spec than it makes sense in normal operation. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2650 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/mips-defs.h')
-rw-r--r--target-mips/mips-defs.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index 8b29e8b2d4..14043be272 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -19,4 +19,9 @@
#define TARGET_LONG_BITS 32
#endif
+/* Strictly follow the architecture standard: Disallow "special"
+ instruction handling for PMON/SPIM, force cycle-dependent
+ Count/Compare maintenance. */
+//#define MIPS_STRICT_STANDARD 1
+
#endif /* !defined (__QEMU_MIPS_DEFS_H__) */