aboutsummaryrefslogtreecommitdiff
path: root/target-mips/machine.c
diff options
context:
space:
mode:
authorLeon Alrae <leon.alrae@imgtec.com>2015-04-14 10:09:38 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2015-06-12 09:05:20 +0100
commite117f52636d04502fab28bd3abe93347c29f39a5 (patch)
treea65867066aff35a198c54440608cf52515587589 /target-mips/machine.c
parentcd0d45c40133ef8b409aede5ad8a99aeaf6a70fe (diff)
downloadqemu-arm-e117f52636d04502fab28bd3abe93347c29f39a5.tar.gz
target-mips: add CP0.PageGrain.ELPA support
CP0.PageGrain.ELPA enables support for large physical addresses. This field is encoded as follows: 0: Large physical address support is disabled. 1: Large physical address support is enabled. If this bit is a 1, the following changes occur to coprocessor 0 registers: - The PFNX field of the EntryLo0 and EntryLo1 registers is writable and concatenated with the PFN field to form the full page frame number. - Access to optional COP0 registers with PA extension, LLAddr, TagLo is defined. P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode. In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0). env->PABITS value is constant and indicates maximum PABITS available on a core, whereas env->PAMask is calculated from env->PABITS and is also affected by CP0.PageGrain.ELPA. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/machine.c')
-rw-r--r--target-mips/machine.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 559402ccc2..8fa755cd39 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -10,6 +10,7 @@ static int cpu_post_load(void *opaque, int version_id)
restore_fp_status(env);
restore_msa_fp_status(env);
compute_hflags(env);
+ restore_pamask(env);
return 0;
}