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authorLeon Alrae <leon.alrae@imgtec.com>2015-02-20 13:07:45 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2015-03-11 14:13:57 +0000
commit644511117e7ca9f26d633a59c202a297113a796c (patch)
tree1a213779e8c4320e00ef6f24c0a49705aef1ac96 /target-mips/machine.c
parent04cd79625fa4103c5839ba36ad476dd22f7f7557 (diff)
downloadqemu-arm-644511117e7ca9f26d633a59c202a297113a796c.tar.gz
target-mips: add missing MSACSR and restore fp_status and hflags
Save MSACSR state. Also remove fp_status, msa_fp_status, hflags and restore them in post_load() from the architectural registers. Float exception flags are not present in vmstate. Information they carry is used only by softfloat caller who translates them into MIPS FCSR.Cause, FCSR.Flags and then they are cleared. Therefore there is no need for saving them in vmstate. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-mips/machine.c')
-rw-r--r--target-mips/machine.c34
1 files changed, 26 insertions, 8 deletions
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 7fc483969a..7d1fa32e57 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -2,19 +2,39 @@
#include "cpu.h"
+static int cpu_post_load(void *opaque, int version_id)
+{
+ MIPSCPU *cpu = opaque;
+ CPUMIPSState *env = &cpu->env;
+
+ restore_fp_status(env);
+ restore_msa_fp_status(env);
+ compute_hflags(env);
+
+ return 0;
+}
+
/* FPU state */
static int get_fpr(QEMUFile *f, void *pv, size_t size)
{
+ int i;
fpr_t *v = pv;
- qemu_get_be64s(f, &v->d);
+ /* Restore entire MSA vector register */
+ for (i = 0; i < MSA_WRLEN/64; i++) {
+ qemu_get_sbe64s(f, &v->wr.d[i]);
+ }
return 0;
}
static void put_fpr(QEMUFile *f, void *pv, size_t size)
{
+ int i;
fpr_t *v = pv;
- qemu_put_be64s(f, &v->d);
+ /* Save entire MSA vector register */
+ for (i = 0; i < MSA_WRLEN/64; i++) {
+ qemu_put_sbe64s(f, &v->wr.d[i]);
+ }
}
const VMStateInfo vmstate_info_fpr = {
@@ -31,9 +51,6 @@ const VMStateInfo vmstate_info_fpr = {
static VMStateField vmstate_fpu_fields[] = {
VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
- VMSTATE_INT8(fp_status.float_detect_tininess, CPUMIPSFPUContext),
- VMSTATE_INT8(fp_status.float_rounding_mode, CPUMIPSFPUContext),
- VMSTATE_INT8(fp_status.float_exception_flags, CPUMIPSFPUContext),
VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
VMSTATE_END_OF_LIST()
@@ -70,6 +87,7 @@ static VMStateField vmstate_tc_fields[] = {
VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
VMSTATE_UINTTL(CP0_UserLocal, TCState),
+ VMSTATE_INT32(msacsr, TCState),
VMSTATE_END_OF_LIST()
};
@@ -183,8 +201,9 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 5,
- .minimum_version_id = 5,
+ .version_id = 6,
+ .minimum_version_id = 6,
+ .post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
@@ -205,7 +224,6 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINT32(env.current_tc, MIPSCPU),
VMSTATE_UINT32(env.current_fpu, MIPSCPU),
VMSTATE_INT32(env.error_code, MIPSCPU),
- VMSTATE_UINT32(env.hflags, MIPSCPU),
VMSTATE_UINTTL(env.btarget, MIPSCPU),
VMSTATE_UINTTL(env.bcond, MIPSCPU),