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authorPetar Jovanovic <petarj@mips.com>2012-12-06 20:30:35 +0100
committerAurelien Jarno <aurelien@aurel32.net>2013-01-01 11:10:47 +0100
commiteec8972a5bc744eda695a86a984d746c240dff90 (patch)
treeb1d626358872a9c91cbacf2202635d778e55dbb6 /target-mips/dsp_helper.c
parenta795ef8dcb8cbadffc996c41ff38927a97645234 (diff)
downloadqemu-arm-eec8972a5bc744eda695a86a984d746c240dff90.tar.gz
target-mips: Fix incorrect reads and writes to DSPControl register
Upper 4 bits of ccond (bits 31..28 ) of DSPControl register are not used in the MIPS32 architecture. They are used in the MIPS64 architecture. For MIPS32 these bits must be written as zero, and return zero on read. The change fixes writes (WRDSP) and reads (RDDSP) to the register. It also fixes the tests that use these instructions, and makes them smaller and simpler. Signed-off-by: Petar Jovanovic <petarj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/dsp_helper.c')
-rw-r--r--target-mips/dsp_helper.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 14daf91950..acf7ceb1d1 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -3948,7 +3948,11 @@ void helper_wrdsp(target_ulong rs, target_ulong mask_num, CPUMIPSState *env)
if (mask[4] == 1) {
overwrite &= 0x00FFFFFF;
newbits &= 0x00FFFFFF;
+#if defined(TARGET_MIPS64)
newbits |= 0xFF000000 & rs;
+#else
+ newbits |= 0x0F000000 & rs;
+#endif
}
if (mask[5] == 1) {
@@ -3999,7 +4003,11 @@ target_ulong helper_rddsp(target_ulong masknum, CPUMIPSState *env)
}
if (mask[4] == 1) {
+#if defined(TARGET_MIPS64)
temp |= dsp & 0xFF000000;
+#else
+ temp |= dsp & 0x0F000000;
+#endif
}
if (mask[5] == 1) {