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authorPetar Jovanovic <petarj@mips.com>2012-11-26 16:13:21 +0100
committerAurelien Jarno <aurelien@aurel32.net>2012-12-06 08:10:50 +0100
commit34f5606ee101f82a247d09d05644ad2a63c8e342 (patch)
treea7416f9afd7031e08289476bdcbcbaadb8ad318e /target-mips/dsp_helper.c
parent80625b97b52836b944a6438e8e3e9d992e6a00b6 (diff)
downloadqemu-arm-34f5606ee101f82a247d09d05644ad2a63c8e342.tar.gz
target-mips: Fix incorrect code and test for INSV
Content of register rs should be shifted for pos before applying a mask. This change contains both fix for the instruction and to the existing test. Signed-off-by: Petar Jovanovic <petarj@mips.com> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/dsp_helper.c')
-rw-r--r--target-mips/dsp_helper.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index e7949c22c0..fda5f0460b 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \
\
filter = ((int32_t)0x01 << size) - 1; \
filter = filter << pos; \
- temprs = rs & filter; \
+ temprs = (rs << pos) & filter; \
temprt = rt & ~filter; \
temp = temprs | temprt; \
\