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authorPetar Jovanovic <petarj@mips.com>2012-12-05 00:29:10 +0100
committerAurelien Jarno <aurelien@aurel32.net>2012-12-06 08:12:14 +0100
commit19e6c50d2d843220efbdd3b2db21d83c122c364a (patch)
tree1ab4c57927dad1533eb0235c3b92f3293d62ef9e /target-mips/dsp_helper.c
parent34f5606ee101f82a247d09d05644ad2a63c8e342 (diff)
downloadqemu-arm-19e6c50d2d843220efbdd3b2db21d83c122c364a.tar.gz
target-mips: Fix incorrect shift for SHILO and SHILOV
helper_shilo has not been shifting an accumulator value correctly for negative values in 'shift' field. Minor optimization for shift=0 case. This change also adds tests that will trigger issue and check for regressions. Signed-off-by: Petar Jovanovic <petarj@mips.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/dsp_helper.c')
-rw-r--r--target-mips/dsp_helper.c17
1 files changed, 9 insertions, 8 deletions
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index fda5f0460b..14daf91950 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -3814,17 +3814,18 @@ void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env)
rs5_0 = rs & 0x3F;
rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
- rs5_0 = MIPSDSP_ABS(rs5_0);
+
+ if (unlikely(rs5_0 == 0)) {
+ return;
+ }
+
acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
- if (rs5_0 == 0) {
- temp = acc;
+
+ if (rs5_0 > 0) {
+ temp = acc >> rs5_0;
} else {
- if (rs5_0 > 0) {
- temp = acc >> rs5_0;
- } else {
- temp = acc << rs5_0;
- }
+ temp = acc << -rs5_0;
}
env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32);