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authorPetar Jovanovic <petar.jovanovic@imgtec.com>2013-05-13 17:14:35 +0200
committerAurelien Jarno <aurelien@aurel32.net>2013-05-19 15:16:20 +0200
commit118d1e4f59c36078a0d76d090d4c16deace47233 (patch)
treef7ef4fc563b88dfec72e3d12ab63df5ffaf6f29b /target-mips/dsp_helper.c
parent0ba365f4a9752a82502e829a3e8cb5f03a1ffc0c (diff)
downloadqemu-arm-118d1e4f59c36078a0d76d090d4c16deace47233.tar.gz
target-mips: set carry bit correctly in DSPControl register
First we need to clear the bit and then we set the given value. Instruction ADDSC sets the bit and instruction ADDWC uses this bit. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/dsp_helper.c')
-rw-r--r--target-mips/dsp_helper.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 655dc8a944..918a898699 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -54,9 +54,10 @@ static inline void set_DSPControl_overflow_flag(uint32_t flag, int position,
env->active_tc.DSPControl |= (target_ulong)flag << position;
}
-static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env)
+static inline void set_DSPControl_carryflag(bool flag, CPUMIPSState *env)
{
- env->active_tc.DSPControl |= (target_ulong)flag << 13;
+ env->active_tc.DSPControl &= ~(1 << 13);
+ env->active_tc.DSPControl |= flag << 13;
}
static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env)
@@ -1267,7 +1268,7 @@ SUBUH_QB(subuh_r, 1);
target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
{
uint64_t temp, tempRs, tempRt;
- int32_t flag;
+ bool flag;
tempRs = (uint64_t)rs & MIPSDSP_LLO;
tempRt = (uint64_t)rt & MIPSDSP_LLO;