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authorLeon Alrae <leon.alrae@imgtec.com>2015-06-04 17:00:31 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2015-06-11 10:13:29 +0100
commitce9782f40ac16660ea9437bfaa2c9c34d5ed8110 (patch)
tree359405ef71ce11ab76a77c82450f9af82f0c687e /target-mips/cpu.h
parentadc370a48fd26b92188fa4848dfb088578b1936c (diff)
downloadqemu-arm-ce9782f40ac16660ea9437bfaa2c9c34d5ed8110.tar.gz
target-mips: add ERETNC instruction and Config5.LLB bit
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit that is set by execution of an LL instruction, and thus when placed between an LL and SC sequence, will never cause the SC to fail. Presence of ERETNC is denoted by the Config5.LLB. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/cpu.h')
-rw-r--r--target-mips/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 03eb888361..2c68782763 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -466,6 +466,7 @@ struct CPUMIPSState {
#define CP0C5_UFE 9
#define CP0C5_FRE 8
#define CP0C5_SBRI 6
+#define CP0C5_LLB 4
#define CP0C5_UFR 2
#define CP0C5_NFExists 0
int32_t CP0_Config6;