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authorYongbok Kim <yongbok.kim@imgtec.com>2016-03-15 09:59:27 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2016-03-30 09:13:59 +0100
commitc870e3f52cac0c8a4a1377398327c4ff20d49d41 (patch)
tree2756e94fce28c6ca90448734ea62d66e20b9b80f /target-mips/cpu.h
parent8e7e8a5b7b95c143f396f6aadd310e9ff2f7efd3 (diff)
downloadqemu-arm-c870e3f52cac0c8a4a1377398327c4ff20d49d41.tar.gz
target-mips: add CMGCRBase register
Physical base address for the memory-mapped Coherency Manager Global Configuration Register space. The MIPS default location for the GCR_BASE address is 0x1FBF_8. This register only exists if Config3 CMGCR is set to one. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: move CMGCR enabling to a separate patch] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/cpu.h')
-rw-r--r--target-mips/cpu.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 4f3ebb9dbb..55d3224291 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -395,6 +395,7 @@ struct CPUMIPSState {
target_ulong CP0_EPC;
int32_t CP0_PRid;
int32_t CP0_EBase;
+ target_ulong CP0_CMGCRBase;
int32_t CP0_Config0;
#define CP0C0_M 31
#define CP0C0_K23 28
@@ -437,7 +438,7 @@ struct CPUMIPSState {
int32_t CP0_Config3;
#define CP0C3_M 31
#define CP0C3_BPG 30
-#define CP0C3_CMCGR 29
+#define CP0C3_CMGCR 29
#define CP0C3_MSAP 28
#define CP0C3_BP 27
#define CP0C3_BI 26