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authorMaciej W. Rozycki <macro@codesourcery.com>2014-11-04 15:37:17 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2014-12-16 12:45:19 +0000
commit8280b12c0e4b515d707509dde4ddde05d9bda4ef (patch)
treea53151b132524028413ea07e89cda67d60a17d10 /target-mips/cpu.h
parent36b86e0dc2be93fc538fe7e11e0fda1a198f0135 (diff)
downloadqemu-arm-8280b12c0e4b515d707509dde4ddde05d9bda4ef.tar.gz
target-mips: Make CP0.Config4 and CP0.Config5 registers signed
Make the data type used for the CP0.Config4 and CP0.Config5 registers and their mask signed, for consistency with the remaining 32-bit CP0 registers, like CP0.Config0, etc. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/cpu.h')
-rw-r--r--target-mips/cpu.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index c01bbdac2d..a08c2c8467 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -446,8 +446,8 @@ struct CPUMIPSState {
#define CP0C3_MT 2
#define CP0C3_SM 1
#define CP0C3_TL 0
- uint32_t CP0_Config4;
- uint32_t CP0_Config4_rw_bitmask;
+ int32_t CP0_Config4;
+ int32_t CP0_Config4_rw_bitmask;
#define CP0C4_M 31
#define CP0C4_IE 29
#define CP0C4_KScrExist 16
@@ -456,8 +456,8 @@ struct CPUMIPSState {
#define CP0C4_FTLBWays 4
#define CP0C4_FTLBSets 0
#define CP0C4_MMUSizeExt 0
- uint32_t CP0_Config5;
- uint32_t CP0_Config5_rw_bitmask;
+ int32_t CP0_Config5;
+ int32_t CP0_Config5_rw_bitmask;
#define CP0C5_M 31
#define CP0C5_K 30
#define CP0C5_CV 29