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authorLeon Alrae <leon.alrae@imgtec.com>2014-09-11 16:28:17 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2015-06-12 09:05:31 +0100
commit5204ea79ea739b557f47fc4db96c94edcb33a5d6 (patch)
tree6b439e0077f4624a23b47ec81770e4debda4cf9c /target-mips/cpu.h
parente117f52636d04502fab28bd3abe93347c29f39a5 (diff)
downloadqemu-arm-5204ea79ea739b557f47fc4db96c94edcb33a5d6.tar.gz
target-mips: add MTHC0 and MFHC0 instructions
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers. In MIPS64, when CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate functions for EntryLo0 and EntryLo1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/cpu.h')
-rw-r--r--target-mips/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index c266e9ff71..474a0e327d 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -473,6 +473,7 @@ struct CPUMIPSState {
#define CP0C5_UFE 9
#define CP0C5_FRE 8
#define CP0C5_SBRI 6
+#define CP0C5_MVH 5
#define CP0C5_LLB 4
#define CP0C5_UFR 2
#define CP0C5_NFExists 0