path: root/target-mips/cpu.h
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authorLeon Alrae <leon.alrae@imgtec.com>2016-03-25 13:49:30 +0000
committerLeon Alrae <leon.alrae@imgtec.com>2016-03-30 09:14:00 +0100
commit34fa7e83e117cb061a9ff5e53a9863b9bfb5f2f6 (patch)
treeb491f54365b6e750e1cf7607ffc3355130d45dc0 /target-mips/cpu.h
parenta9a95061715ca09abff56a3f239f704c410912c2 (diff)
hw/mips: implement ITC Configuration Tags and Storage Cells
Implement ITC as a single object consisting of two memory regions: 1) tag_io: ITC Configuration Tags (i.e. ITCAddressMap{0,1} registers) which are accessible by the CPU via CACHE instruction. Also adding MemoryRegion *itc_tag to the CPUMIPSState so that CACHE instruction will dispatch reads/writes directly. 2) storage_io: memory-mapped ITC Storage whose address space is configurable (i.e. enabled/remapped/resized) by writing to ITCAddressMap{0,1} registers. ITC Storage contains FIFO and Semaphore cells. Read-only FIFO bit in the ITC cell tag indicates the type of the cell. If the ITC Storage contains both types of cells then FIFOs are located before Semaphores. Since issuing thread can get blocked on the access to a cell (in E/F Synchronized and P/V Synchronized Views) each cell has a bitmap to track which threads are currently blocked. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/cpu.h')
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 63fea676a0..725aaef4c2 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -603,6 +603,7 @@ struct CPUMIPSState {
const mips_def_t *cpu_model;
void *irq[8];
QEMUTimer *timer; /* Internal timer */
+ MemoryRegion *itc_tag; /* ITC Configuration Tags */
#include "cpu-qom.h"