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authorLeon Alrae <leon.alrae@imgtec.com>2015-09-14 13:51:31 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2015-10-29 16:16:44 +0000
commit2dcf7908d9e0274c08911400beb7ed14276bb170 (patch)
tree31852b7fb89257870cb1ce5a96e9f703183efb72 /target-mips/cpu.h
parent7540a43a1d9de71fa7a53ccd2bb24a04e2aace41 (diff)
downloadqemu-arm-2dcf7908d9e0274c08911400beb7ed14276bb170.tar.gz
target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6
Implement the relationship between CP0.Status.KX, SX and UX. It should not be possible to set UX bit if SX is 0, the same applies for setting SX if KX is 0. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/cpu.h')
-rw-r--r--target-mips/cpu.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 3799d26d22..c68681dec8 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -1001,7 +1001,12 @@ static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
if (env->insn_flags & ISA_MIPS32R6) {
bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
-
+#if defined(TARGET_MIPS64)
+ uint32_t ksux = (1 << CP0St_KX) & val;
+ ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
+ ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
+ val = (val & ~(7 << CP0St_UX)) | ksux;
+#endif
if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
mask &= ~(3 << CP0St_KSU);
}