aboutsummaryrefslogtreecommitdiff
path: root/target-mips/cpu.h
diff options
context:
space:
mode:
authorLeon Alrae <leon.alrae@imgtec.com>2015-06-09 17:14:13 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2015-06-12 09:05:00 +0100
commit284b731a6ae47b9ebabb9613e753c4d83cf75dd3 (patch)
tree24043a79d29416582fa2489c32419e111715474b /target-mips/cpu.h
parentb435f3f3d174721382b55bbd0c785ec50c1796a9 (diff)
downloadqemu-arm-284b731a6ae47b9ebabb9613e753c4d83cf75dd3.tar.gz
target-mips: extend selected CP0 registers to 64-bits in MIPS32
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32. Introduce gen_move_low32() function which moves low 32 bits from 64-bit temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on MIPS32. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/cpu.h')
-rw-r--r--target-mips/cpu.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 2c68782763..4b81798a18 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -34,7 +34,7 @@ struct r4k_tlb_t {
uint_fast16_t RI0:1;
uint_fast16_t RI1:1;
uint_fast16_t EHINV:1;
- target_ulong PFN[2];
+ uint64_t PFN[2];
};
#if !defined(CONFIG_USER_ONLY)
@@ -225,7 +225,7 @@ struct CPUMIPSState {
uint32_t SEGBITS;
uint32_t PABITS;
target_ulong SEGMask;
- target_ulong PAMask;
+ uint64_t PAMask;
int32_t msair;
#define MSAIR_ProcID 8
@@ -273,8 +273,8 @@ struct CPUMIPSState {
#define CP0VPEOpt_DWX2 2
#define CP0VPEOpt_DWX1 1
#define CP0VPEOpt_DWX0 0
- target_ulong CP0_EntryLo0;
- target_ulong CP0_EntryLo1;
+ uint64_t CP0_EntryLo0;
+ uint64_t CP0_EntryLo1;
#if defined(TARGET_MIPS64)
# define CP0EnLo_RI 63
# define CP0EnLo_XI 62
@@ -472,11 +472,11 @@ struct CPUMIPSState {
int32_t CP0_Config6;
int32_t CP0_Config7;
/* XXX: Maybe make LLAddr per-TC? */
- target_ulong lladdr;
+ uint64_t lladdr;
target_ulong llval;
target_ulong llnewval;
target_ulong llreg;
- target_ulong CP0_LLAddr_rw_bitmask;
+ uint64_t CP0_LLAddr_rw_bitmask;
int CP0_LLAddr_shift;
target_ulong CP0_WatchLo[8];
int32_t CP0_WatchHi[8];
@@ -503,7 +503,7 @@ struct CPUMIPSState {
#define CP0DB_DSS 0
target_ulong CP0_DEPC;
int32_t CP0_Performance0;
- int32_t CP0_TagLo;
+ uint64_t CP0_TagLo;
int32_t CP0_DataLo;
int32_t CP0_TagHi;
int32_t CP0_DataHi;